`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2018/05/23 13:59:45
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module uart_tx( input wire clk,
input wire receive_ack,
input wire [:]data_o,
output reg txd ); localparam IDLE = ,
SEND_START = ,
SEND_DATA = ,
SEND_END = ; reg txd = ; reg [:]cur_st = ;
reg [:]nxt_st = ;
always @(posedge clk)
begin
cur_st <= nxt_st;
end always @(*)
begin
nxt_st = cur_st; case(cur_st) IDLE:
begin
if(receive_ack)
nxt_st = SEND_START;
end SEND_START:
begin
nxt_st = SEND_DATA;
end //每次发送是8bit
SEND_DATA:
begin
if(count == )
nxt_st = SEND_END;
end SEND_END:
begin
if(receive_ack)
nxt_st = SEND_START;
end default:
begin
nxt_st = IDLE;
end endcase
end reg [:]count = ;
always @(posedge clk)
begin
if(cur_st == SEND_DATA)
count <= count + 'b1; else if(cur_st == IDLE || cur_st == SEND_END)
count <= ;
end reg [:]data_o_tmp = ;
always @(posedge clk)
begin
if(cur_st == SEND_START)
data_o_tmp <= data_o; // 在开始状态，采集数据 else if(cur_st == SEND_DATA) //在发送状态，对暂存数据进行右移操作
data_o_tmp[:] <= data_o_tmp[:];
end always @(posedge clk)
begin
if(cur_st == SEND_START)
txd <= ; else if(cur_st == SEND_DATA)
txd <= data_o_tmp[]; //在发送状态，发送最低位 else if(cur_st == SEND_END)
txd <= ;
end endmodule /* add_force {/uart_tx/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/uart_tx/data_o} -radix hex {ab 0ns}
add_force {/uart_tx/receive_ack} -radix hex {1 0ns} */
仿真结果：
